半導體製程導論

第十章 Oxidation

重點

• 氧化層薄膜的應用 (表10.1)
• 乾式與濕式氧化
• 氧化成長模型

內容摘錄

Intro

Grown oxide layer

• 外加
  • high-purity oxygen
• 環境
  • elevated-temperature
  • the diffusion area of the wafer fab
• 反應
  • react with the silicon substrate

Deposited mtd

• 外加
  • external silicon source
• 環境
  • a chamber
• 反應
  • form a thin film on the wafer surface

自己的小畫線

Grown的方法在反應時會消耗原有silicon，而deposit就不會。
命名會取"grow"的原因: indicate that temperature is used to cause the oxide to grow out of the silicon semiconductor material, actually consuming silicon in the process.

氧化層薄膜 oxide film

• T between 750°C to 1100°C
• also referred to as thermal oxide or thermal silicon dioxide
• Another term for silicon dioxide is glass.
• Silicon dioxide is a dielectric material and will not conduct electricity

Nature of Oxide Film

• silicon surface exposed to
  $\to$ amorphous silicon dioxide grows
• atomic structure of this film = 4 with 1 (tetrahedron cell)
  
• melting T of 1732°C grown intrinsic(pure) glass
  • 性質
    • strong adhesion
    • exhibits excellent dielectric properties
    • Over time, the native oxide layer will thicken to an upper limit of about 40Å
  • 問題
    • nonuniform
    • usually a contaminant

氧化層薄膜的應用

• 氧化層的重要性
  • 易於形成
  • excellent interface with the underlying silicon material
• Diff ways in which an oxide layer is used to fabricate a microchip are:
  1. Device scratch protection and contaminant isolation
  2. impurity-mask barrier during doping
  3. Dielectric layer between metal conductor layers

Uniform oxide growth (乾式/濕式氧化)

Dry Oxidation

The time and quality of this reaction varies and is affected by the purity of oxygen gas supplied to the silicon wafer surface and the reaction temperature

• The reaction rate is increased with an increase in temperature

Wet Oxidation

When water is introduced into the rxn
the rate of theoxidation reaction is increased further

• it produces a silicon dioxide film and hydrogen gas
  因氫分子易被氧化層捕捉，使其相較dry oxygen來說較不緻密。

Oxidation Growth Model

氧化層的成長是由氧氣通過氧化層與矽晶片的界面來控制和限制的。為了繼續生長氧化層，氧氣必須與矽晶片接觸。
然而，氧化層將氧氣與矽晶片隔開。氧化層的生長是在氧氣分子通過現有的矽氧化物層到矽晶片時發生的。
這種運動被稱為擴散(更準確地說，是氣體通過固體屏障的擴散性)。擴散是一種物質通過另一種物質的運動。

Diffusion of Oxygen Through the Oxide Layer

Consumption of Silicon during Oxidation

HW

1. Q10.1: What is the difference between a grown and deposited oxide layer
   Ans here
   A grown oxide layer occurs on a wafer by providing externally supplied high-purity oxygen in an elevated-temperatureenvironment to react with the silicon fab.
   A deposited oxide later is generated by using an external silicon source and O2 and reacting these materials in a chamber toform a thin film on the wafer surface.

2. Q10.12: State the chemical reaction for dry oxidation. At what temperature range does this reaction usually take place?
   Ans here

   • 750°C to 1100°C

3. Q10.15: What is diffusion? How does this occur in thermal oxidation?
   Ans here
   Diffusion is the movement of one material through another. Atoms diffuse from regions of high concentration to regions of low concentration for solid, liquid or gas states.
   Diffusion of oxygen atoms occurs during thermal oxidation.

第十一、十二章 Deposition

重點

• 多層金屬化定義
• 薄膜所需特性
• 薄膜沉積
  • CVD系統: APCVD、LPCVD、PECVD
  • PVD - 蒸鍍、濺鍍

內容摘錄

簡介早期的設計、裝配半導體

The design and fabrication of early semiconductor consist of :

1. fabricating the semiconductor devices in silicon
2. interconnecting the devices to one metal conducting layer sandwiched between silicon dioxide as the dielectric material
   
   • This technology was an extension of the first planar transistors made in the SSI era
   • The critical dimension was well over one micron
   • wafer表面不平整

• 隨著科技進步，需要新的金屬導體來維持電性上的表現(electrical performance)
• 先進的介電材料在金屬薄膜間沉積，提供了更足夠的絕緣保護

Film Terminology

Multilevel metallization:
指連接晶圓上高密度金屬與介電層，金屬層間是已介電層薄膜中的開口(vias)連接。(如果沒介電絕緣的保護會發生短路)
vias:
The metal layers are connected by openings in the dielectric film.

Metal & Dielectric Layers

Metal Layers

• Aluminum metalization is the use of aluminum alloy for interconnect wiring
• Al metal deposited on entire surface of the wafer in a solid thin film and then etched to define the width and spacing of the interconnect lines
• Each metal layer can be referred to as Metal-1, Metal-2, and so on.
• Critical layers are those meal layers with linewidths etched to the critical dimension of the device
• Crital layer are sensitive to particulate contamination (killer defects) and reliability issues such as electromigration are more pronounced in fine geometry linewidths

是沈積鋁金屬固態薄膜在蝕刻出寬度、間距。用metal-1,metal-2稱每一層。臨界層(critical layers)的線寬就是臨界尺寸，對污染、電遷移敏感。

Dielectric Layers

• The dielectric layer between the active devices in silion and the first metal layer is termed the first interlayer dielectric (ILD-1)
• The important function of the ILD-1 layer is to isolated transistor devices in two ways:
  • Elecrically from the metal interconnect layers
  • Physically from contamination sources such as mobile ions
• The interlayer dielectric (ILD) is used between different metal layers in the device
  • Serves as an insulating film between two conducting metals or adjacent metal line
  • It has traditionally been silicon dioxide () with a dielectric constant of around 3.9 to 4.0
• A thin film is a thin, solid layer of a meterial created on a substrate
  • 如果一個固體材料有3D(長、寬、厚度)，a thin solid film 就有其中一維(通常是厚度)，而且比另外兩個小很多
  • Thin-film 綁在wafer substrate上(通常比film厚許多)
  • 因為離substrate很近，對薄膜材料會有物理、機械、化學、電性上的影響
    

矽主動元件和metal-1之間的介電質稱為第一介電質(first interlayer dielectric, IDL-1)， IDL-1的功用是對金屬內連線層作電性隔離和對可移動離子之污染源作物理性隔離。IDL傳統是用SiO2，介電系數3.9~4。

Film Deposition

The Film Characteristics

• Good step coverage (薄膜階梯覆蓋)

  薄膜需要表面厚度均勻，若薄膜超出階梯太多會導致高應力、電性短路或不希望產生的感應電荷。

• Ability to fill high aspect ratio gaps (conformality)

  能填的深寬比高，能填滿越深越窄的洞，如介電質的介電孔和淺溝渠(STI)。

• Good thickness unifotmity

  需要薄膜厚度均勻，若薄膜厚度不均勻會導致電性不均勻。

Film-Step Coverage

• It is desirable for thin films to maintain a uniform thickness over surface features
• If the film thins excessively at a step, this can cause high stress, electrical shorts, or undesirable induced charges in the device
  

High Aspect Ratio Gaps

• A small gep (trench or hole) is characterized by its aspect ratio, which is defined as the ration of its depth to width
• Aspect ratio is expressed as a ratio, such as 2:1, which in this case means the gap depth is two times the width
• Examples of gaps that require effective gap-fill capability are vias passing through the interlayer dielectric (ILD) and trenches for shallow trench isolation (STI)
  

Film Growth

• A deposited film grows in three distinct stages
  1. 成核(nucleation)，即形成穩定核團，原子或分子結合成小塊狀。
  2. 塊狀核團晶粒聚結(nuclei coalescence)，稱為島成長(island growth)。任意方向的島核團成長是和表面移動率和合團密度有關。
  3. 連續薄膜(continuous film)，沿著基板表面延伸形成固態薄膜。

Stages of Film Growth

Techniques of Film Deposition

Chemical Vapor Deposition (化學氣相沈積)

化學氣相沈積是藉由氣體混合物之化學反應在晶圓表面上沈積固態薄膜，效果比物理氣相沈積好，有較高深寬比。
The Essential Aspect of CVD

1. Chemical action is involved, either through chemicalreaction or by thermal decomposition (referred to aspyrolysis).
2. All material for the thin film is supplied by an external source.
3. The reactants in a CVD process must start out in the vapor phase (as a gas).

   3個黑體關鍵字考試要寫到

Schematic of CVD Transport and Reaction Steps

Types of CVD Reactors and Principal Characterictics

APCVD (Atmospheric Pressure CVD)

• the reactor must be designed to have optimum reactant gas flow to every wafer in the system. (必須設計成讓最佳反應氣體能通到系統內每片wafer)
• These equipment designs use a belt or conveyor to carry the wafer samples through the reactor gases, which flow through the center of the reactor.
• Continuous-processing APCVD systems have
  • high equipment throughput, good uniformity
  • the capability to process large-diameter wafers
• APCVD systems do have problems with
  • high gas consumption
  • often need frequent reactor cleaning

    Since film deposition also takes place on the conveyor as well as the wafer, the belt transport system must be cleaned (sometimes it is incleaned in situ, or during use)

  • deposited films often exhibit poor step coverage

Low pressure CVD (LPCVD)

• LPCVD are more common now than APCVD because of their
  • lower cost
  • higher production throughput
  • superior film properties
• LPCVD operates at a medium vacuum (about 0.1 to 5 torr), and employs temperatures between 300 and 900°C
• The LPCVD reactor design favors the hot-wall reactor type so that uniform temperature control is achievable over a large operating length
• Since LPCVD reactors are often hot wall, particles deposit on the reactor wall
• Hot-wall reactors require periodic reaction chamber cleanup of particlesby routine maintenance

Plasma-Assisted CVD

• relies on plasma energy, in addition to thermal energy, to initiate and sustain the chemical reactions necessary for CVD
• The advantages of using plasma during CVD are:
  1. Lower processing temperature (250 - 450C)
  2. Excellent gap-fill for high aspect ratio gaps (with high density plasma)
  3. Good film adhesion to the wafer
  4. High deposition rates
  5. High film density due to low pinholes and voids

Film Formation

• The plasma-assisted CV reaction necessary to form a film occurs when RE power is used to break up gas molecules in a vacuum
• The wafer is usually heated in order to assist the surface reactions and reduce the level of undesirable contaminants, such as hydrogen.

Plasma-Enhanced CD (PECVD)

• The development of plasma-enhanced CVD (PECVD) uses plasma energy to create and sustain the CVD reaction.
• The important difference is the much lower PECVD deposition temperature.

  For instance, silicon nitride (Si,N,) is depositedusing LPCVD at 800 to 900°C, yet cannot be deposited over aluminum metallization because Almelts at 660°C. On the other hand, silicon nitride deposited with PECVD at a temperature of 350°Cis suitable for this application

• A PECVD reactor is typically a cold-wall plasma reactor, with the wafer heated in its chuck while the remaining parts of the reactor are unheated
• Deposition parameters must be controlled to ensure the temperature gradient does not affect the film thickness uniformity
• Cold-wall reactors create fewer particles and require less downtime for cleaning

Film Formation during Plasma-Based CVD

PECVD

Physical Vapor Deposition (物理氣相沈積)

• covers two major methods:
  • evaporation
  • sputtering
• Evaporation is used primarily for metals. The surface of a metal sample held in a crucible is heated with an incident electron beam. 蒸發主要用於金屬。在保持在坩堝中的金屬樣品的表面用入射電子束加熱。
  The flux of vapor atoms from the crucible is allowed to reach the wafer. 蒸發主要用於金屬。在保持在坩堝中的金屬樣品的表面用入射電子束加熱。允許來自坩堝的蒸氣原子通過到晶圓。
• Such evaporation must be done under high-vacuum conditions. 這種蒸發必須在高真空條件下進行。
• Evaporation with an e-beam is quite directional, allowing interesting shadowing effects to be used. 電子束蒸發是非常定向的，允許使用有趣的遮蔽效應。

• Sputtering is a process in which chemically inert atoms, such as argon, are ionized in a glow discharge (also called a plasma) 激發氣體中的原子，例如氬氣，以產生電漿
• The ions are accelerated into a target by the electric field in the so-called dark space at the boundary of the plasma 電漿邊界的所謂“暗空間”中，離子被電場加速到靶上
• Atoms from the target are knocked out (the sputtering process), and these atoms are allowed to reach the substrate 靶上的原子被擊出（濺射過程），並且這些原子被允許到達基板
• Sputtering takes place in a low-pressure gas environment 濺射發生在低壓氣體環境中
• It is less directional than e-beam evaporation and typically can achieve much higher deposition rates. 它比電子束蒸發更不方向性，並且通常可以實現更高的沉積速率

HW

1. Q11.5: Define the aspect ratio. Why is a high-aspect ratio important for ULSI devices?
   Ans here
   The aspect ratio of a small gap is defined as the ratio of its depth to width. The aspect ratio is important because the ability to fill very small gaps and holes on the surface of the wafer has become one of the most important film characteristics for devices.

2. Q11.6: List and describe three stages of film growth.
   Ans here

   1. Nucleation: clusters of stable nuclei are formed,
   2. nuclei coalescence: also referred to as island growth where randomly oriented island clusters grow based on surface mobility, and
   3. continuous film: where the island clusters meet and form a solid sheet that spreads across the substrate surface.

第十三章 Photolithography: Surface Preparation to Soft Bake

重點

• 微影之基本觀念，包括製程、DC、光頻譜、解析度及曝光度。
• 正及負雕像術之差異。
• 微影8個基本步驟。
• 正及負光阻的物理性質。
• 傳統i-line光阻的化學性及應用。
• 深紫外光（DUV）光阻的化學性及優點。

內容摘錄

基本觀念

• Photolithography produces a three-dimensional pattern on the surface of the wafer using a light-sensitive photoresist material and controlled exposure to light.
• photolithography別稱：photo, lithography, masking, and patterning.

Photolithography Concepts

• Patterning Process
  • Photomask
  • Reticle
• Critical Dimension Generations
• Light Spectrum
• Resolution

reticle 和 mask 間的區別

reticle

1. 搭配固定機(stepper)
2. 有reduction less (當UV光穿過的時候會將光做倍率縮放，投影在wafer上面積會比在reticle上面積小
3. 有1顆die或4顆die的設計(layout)
4. 4:1的比例：若reticle上面線寬4mm那wafer上只剩1mm

mask

1. 搭配接觸/進階式曝光機(Contact/Proximity Aligner System)
2. mask多大wafer上曝光的面積就有多大
3. 1:1的比例

   可能考：請說明兩者間的差別還有在Photolithography上面使用的時候各自優缺點。

Light Spectrum

光譜能量對激發光阻和從reticle轉移圖案到wafer上面是必要的。能量的來源是輻射，通常是紫外線光源。

Resolution

Resolution是能夠區分wafer表面上兩個接近的特徵的能力。

曾經考過

Important Wavelengths for Photolithography Exposure

Photolithography Processes

• Negative Resist (負光阻)

  • wafer上面的圖案跟mask上面的圖案是相反的
  • 曝光的光阻變硬且不溶於溶劑
  • 顯影劑移除未曝光的光阻
    

• Positive Resist (正光阻)

  • mask上面的圖案跟wafer上面的圖案是相同的
  • 曝光的光阻變軟且溶於溶劑
  • 顯影劑移除曝光的光阻
    

Eight Steps of Photolithography

期末考很常出現：問答、給圖說明步驟

Step 1: Vapor Prime

第一步驟是清潔、脫水、並且在wafer表面上塗上一層薄薄的光阻。這些步驟的目的是促進光阻和wafer表面的附著力。
在脫水烘烤(用氣體的方式蒸塗在wafer表面)，wafer會被HMDS(六甲基二矽氮烷)所處理，它會增加光阻和wafer表面的附著力

Step 2: Spin Coat

這個步驟是將液體光阻材料用旋轉塗布的方式塗佈在wafer上面。
wafer會被放在真空吸盤上面，真空吸盤是一個平的金屬或是塑膠盤，上面有小小的真空孔來固定wafer。
然後wafer會被旋轉來獲得一個均勻的光阻塗佈在wafer上面。
會有一些設定好的參數，如轉速、

Process Summary

• Wafer is held onto vacuum chuck
• Dispense ~ 5ml of photoresist
• Slow spin ~ 500 rpm
• Ramp up to ~ 3000 to 5000 rpm
• Quality measures:
  • time
  • speed
  • thickness
  • uniformity
  • particles and defects

Step 3: Soft Bake

Characteristics of Soft Bake:

• 改善光阻和wafer的附著力
• 促進wafer上的光阻均勻性
• 並在蝕刻過程中產生更好的線寬控制
• 驅除光阻中的大部分溶劑
• 典型的軟烘烤溫度是90到100°C
  • 持續30秒
  • 在hot-plate上
  • 接著放在cold-plate上冷卻

Step 4: Alignment and Exposure(對準和曝光)

mask和wafer會被曝光到控制的UV光源上，將mask上的圖案轉移到wafer上面。

• 轉移圖案到wafer上
• 用UV light曝光

Process Summary:

• 將mask上的圖案轉移到wafer上面
• 激活光阻的光敏成分
• Quality measures 品質控制:
  • linewidth resolution 線寬解析度
  • overlay accuracy 疊合精度
  • particles and defects 顆粒和缺陷

Step 5: Post-Exposure Bake (PEB)

• 如果是用deep UV作為光源一定要做曝後考才能完成曝光顯影動作，其他在傳統上可做可不做。現在漸漸變成都要做
• 深紫外光阻必須做曝後烤
• 典型的溫度是100到110°C
• 曝光後要立即做
• 已成為DUV和標準光阻的標準

Step 6: Develop

Process Summary:

• 光阻可溶區域被顯影劑溶解
• 留下wafer表面上的可見圖案
  • windows
  • islands
• Quality measures:
  • line resolution
  • uniformity
  • particles and defects

Step 7: Hard Bake

需要一個顯影後的熱烘烤，稱為硬烤，以蒸發剩餘的光阻溶劑並改善光阻對晶圓表面的附著力。

• A Post-Development Thermal Bake 顯影後熱烘烤
• Evaporate Remaining Solvent 蒸發剩餘的溶劑
• Improve Resist-to-Wafer Adhesion 改善光阻對晶圓表面的附著力
• Higher Temperature (120 to 140°C) than Soft Bake 比軟烘烤高溫

Develop Inspect

• Inspect to Verify a Quality Pattern 檢查以驗證質量圖案
  • Identify Quality Problems (Defects) 識別質量問題（缺陷）
  • Characterize the Performance of the Photolithography Process 表徵光刻工藝的性能
  • Prevents Passing Defects to Other Areas 防止缺陷傳遞到其他區域
    • Etch
    • Implant
  • Rework Misprocessed or Defective Wafers 重新處理錯誤或有缺陷的晶圓
    Resist-coated Wafers 光阻塗佈的晶圓
• Typically an Automated Operation 通常是自動操作

Photoresist

• Photoresist
  • Types of Photoresist
  • Negative Versus Positive Photoresists
• Photoresist Physical Properties
• Conventional I-Line Photoresists
  • Negative I-Line Photoresists
  • Positive I-Line Photoresists
• Deep UV (DUV) Photoresists

Types of Photoresist

• 負光阻：照到UV光的地方交鏈鍵結會接起來&固化，且不容易溶解在顯影液
• 正光阻：照到UV光的地方會破壞交鏈鍵結
• 負光阻用比較少的原因：沖顯影液時會吸收，然後會讓圖案失真

Photoresist Physical Properties

• Resolution:
  可以辨別做光阻的pattern最小feature size
• Contrast
  
• Sensitivity(PS: 不要跟第一個搞混)
  指單位面積所要提供光阻曝光所需的最小能量(焦耳

  exposure dose(曝光劑量):
  全部(整片)的面積曝光所需的劑量總量

• Adhesion
  how strongly the resist sticks to the substrate. 光阻對基板的附著力
• Etch resistance
  • The resist film must maintain its adhesion and protect the substrate surface from the subsequent wet and dry etch processes. 光阻膜必須保持其附著力並保護基板表面免受後續的濕式和乾式蝕刻過程的影響。
  • This property is known as etch resistance. 這種性質被稱為蝕刻抗性。
• Surface tension
  Resist has molecular forces that create a relatively high surface tension so that the resist molecules hold together during the various process steps. 光阻具有分子力，可以在各種工藝步驟中使光阻分子保持在一起，從而產生相對較高的表面張力。
  At the same time, the surface tension of resist must be low enough to provide for good flow and wafer coverage during application. 同時，光阻的表面張力必須足夠低，以便在應用過程中提供良好的流動性和晶圓覆蓋性。

Negative Resist Cross-Linking

PAC as Dissolution Inhibitor in Positive I-Line Resist

Deep UV (DUV) Photoresists

• i-line wavelength of 365 nm — a CD of 0.35 $\mu m$ was achievable.
• reduce the wavelength of the exposure light source to a value of around 250 nm (0.25 p.m) — a CD of 0.25 um on critical layers
• 248 nm UV wavelength referred to as deep UV (DUV)

Chemical Amplification for DUV Resists:

Chemically Amplified (CA) DUV Resist

HW

1. Q13.1: What is photolithograohy?
   Ans here
   Photolithography produces a three-dimensional pattern on the surface of the wafer using a light-sensitive photoresist material and controlled exposure to light.
   微影是利用光敏的光阻材料及控制其曝光量以在晶圓上產生三維的圖案

2. Q13.5: What is overlay accuracy, and how does this contribute to the mask overlay budget?
   Ans here
   Overlay accuracy is the precise alignment between the pattern on the mask and the existing features on the wafer surface.
   Since multiple masks are used during patterning, any overlay misalignment contributes to the total placement tolerances between the different features on the wafer surface, or mask overlay budget.
   重疊精確：微影須將光罩圖案和已存在晶圓表面尺寸做精確對準
   重疊預算：若重疊未對準使晶圓上不同尺寸間有位置扭曲，此為重疊預算，重疊預算高則會大幅降低電路密度，限制元件尺寸大小和IC特性

3. Q13.7: Explain the difference between negative and positive lithography.
   Ans here
   Negative lithography prints a pattern on the wafer surface that is opposite the pattern in the mask. Positive lithography prints a patternon the wafer that is the same pattern as on the mask.
   負光阻：光阻曝光後其晶圓表面上的圖案和光罩上是相反的，光阻變成不溶解且鍵結硬化

第十四章 Photolithography: Alignment and Exposure

重點

1. 微影中對準及曝光之目的。
2. 曝光光源主要有哪兩種?其激發頻譜有何不同?對CD的影響?
3. 曝光設備，各世代機台的優缺點。
4. 標線板在微雕像中之用途?
5. 對準技術。

內容摘錄

• step-and-repeat
  1. The water is aligned to the reticle so that the pattern can be transferred to the proper location on the wafer surface. 翻譯：晶圓對準光罩，以便將圖案轉移到晶圓表面的正確位置。
  2. Once the best focus and alignment are obtained, a shutter opens to allow UV light to pass from the illuminator to the reticle through a projection lens and then onto the resist-coated wafer. 一旦獲得最佳焦點和對準，快門就會打開，允許紫外線從照明器通過投影鏡頭到光罩，然後到光阻塗層的晶圓上。
  3. Once a pattern is exposed, the stepper will step to the next location on the water and repeat the alignment and exposure. 一旦曝光了一個圖案，步進機就會跳到水面上的下一個位置，並重複對準和曝光。

Reticle Pattern Transfer to Resist

Layout and Dimensions of Reticle Patterns

• 小十字用來做對準，也叫align mark
• 不同層對應不同光照來處理，表上列出每一道光照的圖層

Optical Exposure

• 線寬越小，對曝光光源要求越嚴苛，波長越短

Electromagnetic Spectrum

• 所有可見與不可見的電磁波統稱為電磁頻譜(Electromagnetic Spectrum)
• UV spectrum (4nm~450nm)有以下幾種：
  1. The vacuum ultraviolet (VUV)：157nm
  2. DUV：248nm、193nm
  3. Extreme UV (EUV)：13.5nm
• 必須在黃光下作業

Ultraviolet Spectrum

Optical Lithography

Exposure Sources：

1. Mercury Arc Lamp
   • The high-pressure mercury arc lamp is used as the UV illumination source in all conventional i-line steppers 高壓汞弧燈用作所有傳統i-line stepper的UV照明源
   • the useful UV wavelength emissions for a mercury arc lamp between about 240 nm and 500nm in length 高壓汞弧燈的有用UV波長發射長度約為240nm至500nm之間
2. Excimer Laser
   • light intensity(光強度)：I=power/area 每單位面積功率
   • Expose dose(曝光劑量)=I*t 光強度$\times$曝光時間
   • Energy=ptarea 曝光所需能量

• i-line 的光阻劑量大概 100mJ/cm$^2$
• 在DUV波段要花費太多時間不符成本

Excimer Laser (準分子雷射)

• 主要的好處在於能提供DUV更多的光強彌補mercury arc lamp效率不好的問題
• laser light source: An exotic molecule fromed an atom of a noble gas and halogen (鈍氣分子&鹵素，如ArF)
  

Photolithograhy Equipment

• Contact Aligner
  • 每一次曝光就曝整片wafer
  • 光照和光阻是接觸的(曝光的時候光照放在光阻上)。
    優點：好的解析度
    缺點：會帶來一些汙染、壽命很短
• Proximity Aligner
  • 每一次曝光就曝整片wafer
  • 光照和光阻沒直接接觸，有縫隙
  • UV光前進時會有繞射問題，所以解析度會有一些失真
• Step-and-Repeat Aligner (stepper)
  • 一次只能曝1~4顆
  • 倍率：4X、5X、10X
  • 由於是大到小的比例縮放，更容易fabricate the reticle
    
• Extreme Ultraviolet (EUV) Lithography
• System (not included in the exam

Reticles Materials

• 材料用熔融矽土，好處是很低的熱膨脹係數，即便溫差很大線寬也不會影響
• 光穿透率要好、沒有缺陷
• 上面會鍍鉻膜，因為鉻膜可阻擋UV光前進

Comparison of Reticle Versus Mask

HW

1. Q14.5: Describe the relationship between light exposure wavelength and image resolution.
   Ans here
   曝光波長越短，特徵尺寸解析越小
   曝光波長越短，解析力愈高(能解析的尺寸R越小)

第十五章 Photolithography: Resist Development and Advanced Lithography

重點

1. 傳統與化學倍增式DUV光阻為何與如何執行曝光後烘烤。
2. 分別針對傳統與化學倍增式DUV光阻，描述其負與正光阻顯影製程。
3. 說明為何光阻顯影後，需進行硬烤處理。
4. 解釋顯影後檢查所具有之優點。

內容摘錄

POST-EXPOSURE BAKE

• 使用化學倍增式光阻一定要做曝後烤
• 做的好處：可以改善光阻的adhesion、減少駐波效應

DUV Post-Exposure Bake (PEB)

• 化學倍增式光阻有PAG，做曝後烤可加速酸化反應讓它易溶於顯影液

Chemically Amplified (CA) DUV Resist

Conventional I-Line PEB

• 對於I-Line的光阻來說曝後烤可做可不做
• 用抗反射層，也能減緩當UV光打過去有一部份反射造成線寬波浪形
• Reduction of Standing Wave Effect due to PEB
  

Develop

• Negative Resist
• Positive Resist

Develop

The three primary types of development problems are

1. underdevelopment (顯影不足)
   appears wider than a normal line and will have sloping sidewalls. 顯影不足的線寬會比正常的線寬寬，而且會有斜的側壁。
2. incomplete development (顯影不完全)
   has residual resist on the substrate that should have been removed during develop. 顯影不完全的線寬會有殘留的光阻在基板上，而且會有斜的側壁。
3. overdevelopment (顯影過度)
   removes too much resist causing features to appear narrower and poorly-defined. 顯影過度的線寬會比正常的線寬窄，而且會有斜的側壁。

Negative Resist

• 2$\mu m$以下尺寸的光阻不適用，因為會吸顯影液，造成swelling & distortion

Positive Resist

• the most common resists used in submicron wafer fabrication due to improved linewidth resolution. 由於線寬解析度的提升，正光阻是次微米晶圓製造中最常用的光阻。
• he two general types of positive resists used in wafer microlithography are
  • conventional DNQ i-line resists 傳統DNQ i-line光阻
  • chemically amplified (CA) DUV resists 化學倍增式DUV光阻
• Although these two resists are very different chemically, it is generally truethat phenolic resin is soluble in a base solution. 雖然這兩種光阻在化學上有很大的不同，但是通常酚樹脂是可溶於鹼性溶液的。

Developer

have selectivity(選擇比)

• 對兩種反應的差異很大
• 需要反應的A會反應的很快，相對B就不靈敏
• 如果顯影選擇比很高，顯影效果會比較好

HARD BAKE

• 可以把光阻裡剩餘的solvent去除
• 讓光阻變堅硬 (在之後蝕刻或離子植入時起到保護作用
• 改善光阻和substrate的附著力

DEVELOP INSPECT

在進行蝕刻或離子植入前要經過顯影後檢視看顯影的圖跟設計是否一致
因為到了後面就沒法重做

HW

1. Q15.3: Why is temperature uniformity important for PEB?
   Ans here
   PEB temperature non-uniformity (both in steady-state and transient phases) impacts across-wafer CD uniformity

2. Q15.17: Explain why hard bake is done.
   Ans here

   • 可以把光阻裡剩餘的solvent去除
   • 讓光阻變堅硬 (在之後蝕刻或離子植入時起到保護作用
   • 改善光阻和substrate的附著力

第十六章 Photolithography: Etch

重點

1. 重要的蝕刻參數。
2. 何謂乾蝕刻，優點?
3. 物理性與化學性蝕刻機制。

內容摘錄

Intro

• 可以以物理/化學性方式去除掉晶圓表面不要的材料
• 蝕刻選擇比要高
  

Etch Process

Two basic types of etch processes are used in semiconductor manufacturing:

• dry etch
  • 使用氣體電漿進行蝕刻
  • 以物理(轟擊)的方式去除
  • 開機費貴貴
• wet etch
  • 使用丙酮進行蝕刻
  • 常用強酸去除(例如BOE(緩衝氧化物刻蝕液)，是由氫氟酸、醋酸、磷酸所組合
  • 只能用在大面積尺度，線寬太小蝕刻液會吃不進去

Etch Parameters

Etch rate

• 蝕刻速率=所移除材料的總量(通常以薄膜厚度)/蝕刻時間
• 蝕刻速率與蝕刻液濃度成正比
• loading effects
  在大面積蝕刻蝕時，跟蝕刻液反應會吸收掉蝕刻液的濃度
  最後蝕刻的效率會較慢
  反之在小面積比較不易稀釋蝕刻液，速率較快

Etch profile

Etch profile: refers to the shape of the sidewall of the etched feature. 蝕刻輪廓是指蝕刻特徵的側壁形狀。
分成兩種：

• isotropic(等向性)：
  • 定義：所有方向蝕刻速率都一樣
  • 導致 undercutting(底切現象)，線寬失真
    
  • 常發生在濕蝕刻，不適合去做精確的線寬
• anisotropic(異向性/非等向性)
  • 定義：只在一個方向蝕刻(通常是往下侵蝕)
  • 能精確控制線寬
    
• 乾/濕蝕刻造成的側壁輪廓
  

Etch bias

• 定義：a measure of the change in linewidth or space of a critical dimension (CD) after performing an etch process 蝕刻前後線寬的變化
• 通常由底切所造成抑或是蝕刻輪廓
• 公式：$\text{Etch bias}=W_b-W_a$

  其中，
  $W_b=$ 蝕刻前光阻原來的線寬
  $W_a=$ 蝕刻完光阻移除後最終的線寬

  這邊講了非常多蝕刻的名詞，
  像profile、etch bias都有可能會出現在解釋名詞，所以定義要搞清楚

• overetch
  

Selectivity

• 定義：how much faster one film etches than another film under the same etch conditions 一種薄膜蝕刻速率與另一種薄膜蝕刻速率的比例
• 公式：$\displaystyle S_R=\frac{E_f}{E_r}$

  其中，
  $E_f=$ 進行蝕刻時薄膜的蝕刻速率
  $E_r=$ masking layer的蝕刻速率(e.g 光阻)

• 好的選擇比比例至少100:1以上(想要的比不想要的侵蝕快100倍以上)
  

Uniformity

• 定義：a measure of the capability of the process to etch evenly across the entire surface area of the wafer, across the entire wafer lot, and from lot to lot 蝕刻能力的一種度量，能夠均勻地蝕刻整個晶圓表面積，整個晶圓批次，以及從一批到另一批
  

Dry Etch

Advantages of Dry Etch over Wet Etch

1. Etch profile is anisotropic with excellent control of sidewall profiles 蝕刻輪廓是異向性的，側壁輪廓控制非常好
   乾蝕刻可以選擇氣體來源使薄膜可以形成異向性的蝕刻，對於側壁輪廓的控制就能精確
2. Good CD control
   線寬(CD)控制也非常的好
3. Minimal resist lifting or adhesion problems 最小化光阻掀起或附著力問題
   使光阻不容易掀掉和解決附著力的問題
4. Good etch uniformity within wafer, wafer-to-wafer and lot-to-lot
   乾蝕刻的蝕刻均勻性都很好
5. Lower chemical costs for usage and disposal
   因為濕蝕刻都是用強酸/鹼下去做薄膜侵蝕，必須經過一定程序處理掉

   這五點曾經出現在期末考問答題

Chemical and Physical Dry Etch Mechanisms

HW

1. Q16.1: Define etch. What is the goal of etching?
   Ans here
   Etch is the process of selectively removing unneeded material from the wafer surface by using either chemical or physical means. The goal of etching is to accurately reproduce the mask features on the wafer.

2. Q16.2: What are the two types of etch process? Give a short description of each type.
   Ans here
   Dry etch and wet etch. Dry etch exposes the wafer surface to a plasma created in the gaseous state. The plasma passes through the mask openings and interacts physically or chemically (or both) with the wafer to remove the surface material. Wet etch uses liquid chemicals such as acids, bases and solvents to chemically remove the wafer surface. It is generally applicable to geometries greater than $3\mu m$.

第十七章 Doping Processes

重點

1. 解釋晶圓製作中，摻雜的目的與應用。
2. 討論摻質擴散的原理與製程。
3. 提供有關離子植入之概要說明，包括它的優缺點。
4. 討論題子植入時，有關劑量與範圍的重要性。
5. 解釋何謂離子植入之退火及通道效應。

內容摘錄

intro

• 定義：the introduction of a dopant into the crystal structure of a semiconductor material to modify its electronic properties (e.g., electrical resistivity) 將摻質引入半導體材料的晶體結構中，以修改其電子特性(例如電阻率)
• Dopant species are also referred to as impurities(這是需要雜質的，像是加進去的dopants) but should not be confused with contaminating impurities (不要的稱為汙染物)
• 有兩種技術可將dopant的元素加進wafer中：
  • thermal diffusion
    Thermal diffusion uses high temperature to move the dopant through the silicon lattice structure 熱擴散使用高溫將摻質通過矽晶格結構
    • This method is dependent on time and temperature 這種方法取決於時間和溫度
  • ion implantation
    Ion implantation introduces dopants into the substrate through a high-voltage ion bombardment 離子植入通過高電壓離子轟擊過程將摻質引入基板中
    • The dopants are implanted into the wafer through high-energy collisions at the atomic level 摻質通過原子級的高能碰撞被植入晶圓中

常用dopants

Doped Regions

• 擴散的時候會拿一些元素當作擋罩(圖上是用oxide)
  • 裸露出來的就是要doping的地方
• doping的區域稱作 dopant profile
  
• 在離子植入方面，擋罩通常是光阻
  • 因為溫度低光阻不會被熔融所以能用的擋罩比較多元(相對diffusion在高溫下進行，所以通常只能用oxide/nitride當擋罩

Diffusion

• 物質由高往低濃度移動
• 氣、液、固態都可以發生
• 當高濃度dopant打進wafer會產生固態的擴散
• 不同dopant有著不同的 diffusivity(擴散係數)
  • D越大速度越快
  • 擴散係數隨溫度增加
• 在wafer上dopant有兩種移動的模式：
  • interstitional(間隙式替換)
    用填入空隙的方式進去
    主要進行這模式的元素：Au、Cu、Ni
  • substitutional(替代式替換)
    用替換的方式進去
    主要進行這模式的元素：As、P
    

Solid Solubility(固體溶解度)

定義：At a given temperature, there is a limit to how much dopant can be absorbed by the silicon. This is referred to as the solid solubility limit 在給定溫度下，矽能吸收多少摻質有一個極限。這被稱為固體溶解度極限

• Each a particular dopant has a solid solubility limit
  

Ion implantation

定義：a method for introducing controlled amounts of dopants into the silicon substrate to change its electronic properties. 一種將控制量的摻質引入矽基板中以改變其電子特性的方法。

• 物理反應，
• 沒有極限的問題打多少都沒關係
• 大大大優點：可以精確的控制打進去dopant的濃度和深度

控制dopant濃度/深度

Overview

Ion implant processing is done in one of the most complex semiconductor processing tools, called the ion implanter 離子植入處理是在最複雜的半導體處理工具之一中完成的，稱為離子植入機

1. The implanter has an ion source component that creates positive-charged dopant ions from a source material. 植入機具有離子源組件，該組件從源材料中創建正電荷摻質離子。
2. The ions are extracted and then separated in a mass analyzer to form a beam of the desired dopant ions. 離子被提取，然後在質量分析儀中分離，以形成所需摻質離子的束。
   • The number of ions in the beam is related to the concentration of dopants introduced into the wafer 植入機具有離子源組件，該組件從源材料中創建正電荷摻質離子。
3. The beam of ions is accelerated in a voltage field to attain a high velocity (on the order of 10 cm/sec) 離子束在電壓場中加速，以獲得高速度（大約10 cm / sec）
   • Because of the high velocity, the ions have kinetic energy that is used to implant the dopants into the silicon crystal lattice structure of the target wafer 由於速度很高，因此離子具有用於將摻質植入目標晶圓的矽晶體晶格結構的動能。
4. The beam scans the wafer to provide uniform doping across the wafer surface 離子束掃描晶圓以在晶圓表面提供均勻的摻質
5. Implantation is followed by a thermal anneal step to activate the dopant ions in the crystal structure 植入後，需要熱退火步驟來激活晶體結構中的摻質離子

• All implanter processing is done in a high vacuum 所有植入機處理都在高真空環境中完成
  

Advantages of Ion Implantation(會考很重要無限星星)

1. Precise control of dopant concentration
2. Good dopant uniformity
3. Good control of dopant penetration depth
4. Produces a pure beam of ions
5. Low temperature processing
6. Ability to implant dopants through films
7. No solid solubility limit

Disadvantages of Ion Implant

• 高能量離子束會把原本矽原子位置給打亂，需回復鍵結
• 有兩種能量喪失的形式：
  • Electronic stopping
    Electronic stopping of dopant atoms is caused by interactions with the target electrons, similar to stopping a projectile in a thick medium, such as a child jumping into a pile of plastic balls 摻質原子的電子停止是由於與目標電子的相互作用引起的，類似於在厚介質中停止彈道，例如孩子跳進一堆塑料球
  • Nuclear stopping
    Nuclear stopping of implanted ions is caused by collisions between atoms that cause a displacement of silicon atoms. 植入離子的核停止是由於原子之間的碰撞引起的，這些碰撞導致矽原子的位移。
    • It can be visualized as the collision between two hard spheres, such as billiard balls. 它可以想像為兩個硬球之間的碰撞，例如撞球。
    • Depending on the ion mass and energy, an implanted atom can displace as many as 104 silicon atoms by nuclear collisions before coming to rest 取決於離子質量和能量，植入的原子在停止之前可以通過核碰撞將多達104個矽原子置換。
• 停在多少深度取決於喪失多少能量
  

Annealing

• Ion implantation damages the silicon lattice by knocking atoms out of the lattice structure. 離子植入通過從晶格結構中擊出原子來損壞矽晶體。
• These interstitial dopants are electrically inactive until activated by a high-temperature annealing step. 這些間隙摻質在高溫退火步驟激活之前是電性不活性的。
  • 通常都是在相對高溫+維持一段時間，讓他有足夠的溫度和能量去完成活化的反應，修補這些鍵結
  • Electrical activation of dopants occurs as a function of time and temperature, with longer times and higher temperatures increasing the dopant activation 摻質的電性激活是時間和溫度的函數，隨著時間的增加和溫度的升高，摻質的激活增加
  • There are two basic methods for heating the implanted wafer for anneal: 有兩種基本方法可用於加熱植入的晶圓以進行退火：
    • Furnace anneal 熔爐退火
    • Rapid thermal anneal (RTA) 快速熱退火

Channeing

There are four ways that channeling is controlled during implant: 有四種方法可以在植入期間控制通道：

1. wafer tilt, 1. 晶圓傾斜
2. screen oxide layer 2. 屏幕氧化層
3. preamorphization of the silieen
4. usingdopants with greater amu’s (atomie mass units)

Wafer Tilt

直接把wafer轉下（7度）就比較不會有某一個方向通通不會有能量損失的問題

Screen Oxide Layer

用一層很薄的oxide layer當作screen oxide layer當犧牲層，讓ion beam有能量的損失使其停在較淺介面，做完植入再去除掉犧牲層

HW

1. Q17.1: What is doping?
   Ans here
   Doping is the introduction of a dopant (also known as an impurity) into the crystal structure of a semiconductor material to control its electronic properties (e.g., electrical resistivity)

2. Q17.3: Give a short description of thermal diffusion.
   Ans here
   Thermal diffusion uses high temperature to move the dopant through the silicon lattice structure. This method is dependent on time and temperature

3. Q17.4: Give a short description of ion implantation.
   Ans here
   Ion implantation introduces dopants into the substrate through a high-voltage ion bombardment. The dopants are implanted into the wafer through high-energy collisions at the atomic level

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期末分隔線

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